Exploration of distributed shared memory architectures for NoC-based multiprocessors |
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| Affiliation: | 1. Institute of Digital and Computer Systems, Tampere University of Technology, 33720 Tampere, Finland;2. Computer Engineering, Delft University of Technology, 2628 CD Delft, The Netherlands;3. Sandbridge Technologies, White Plains, NY 10601, USA;1. Departamento de Informática e Ciência da Computação, Instituto de Matemática e Estatística, IME, Universidade do Estado do Rio de Janeiro, Rua São Francisco Xavier, 524, Pavilhão Reitor João Lyra Filho, 6o Andar, Diretoria, Sala 6019, Bloco B, Rio de Janeiro, Rj 20550-900, Brazil;2. Programa de Engenharia de Sistemas e Computação, COPPE, Universidade Federal do Rio de Janeiro, Cidade Universitária, Centro de Tecnologia, Bloco H, Sala 319, Rio de Janeiro, RJ 21941-972, Brazil;3. CRACS & INESC-Porto LA, Faculdade de Ciências, Universidade do Porto, Rua do Campo Alegre, 1021, 4169-007 Porto, Portugal;1. iPack Vinn Excellence Center, School of Information and Communication Technology, Royal Institute of Technology (KTH) Electrum 229, 164 40 Stockholm-Kista, Sweden;2. School of Information Science and Technology, Fudan University, Shanghai, China;1. Department of Computer Science and Technology, Hangzhou Dianzi University, Hangzhou 310018, China;2. Department of Information and Communication Systems, Hohai University, Changzhou 213022, China;3. Institute of Telecommunications, University of Beira Interior, Covilha, Portugal;4. University of ITMO, St. Petersburg, Russia;1. Universidade do Vale do Rio dos Sinos, Rio Grande do Sul, Brazil;2. Instituto Nacional de Telecomunicações, Minas Gerais, Brazil;3. Universidade Federal do Rio Grande do Sul, Rio Grande do Sul, Brazil;1. Software Competence Center Hagenberg, Hagenberg, Austria;2. P&T Connected, Hagenberg, Austria;3. Zhejiang University, UIUC Institute, Haining, China |
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| Abstract: | Multiprocessor system-on-chip (MP-SoC) platforms represent an emerging trend for embedded multimedia applications. To enable MP-SoC platforms, scalable communication-centric interconnect fabrics, such as networks-on-chip (NoCs), have been recently proposed. The shared memory represents one of the key elements in designing MP-SoCs to provide data exchange and synchronization support.This paper focuses on the energy/delay exploration of a distributed shared memory architecture, suitable for low-power on-chip multiprocessors based on NoC. A mechanism is proposed for the data allocation on the distributed shared memory space, dynamically managed by an on-chip hardware memory management unit (HwMMU). Moreover, the exploitation of the HwMMU primitives for the migration, replication, and compaction of shared data is discussed. Experimental results show the impact of different distributed shared memory configurations for a selected set of parallel benchmark applications from the power/-performance perspective. Furthermore, a case study for a graph exploration algorithm is discussed, accounting for the effects of the core mapping and the network topology on energy and performance at the system level. |
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