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Cost/Quality Trade-off in Synthesis for BIST
Authors:P Bukovjan  L Ducerf-Bourbon  M Marzouki
Affiliation:(1) ON Semiconductor, B. Necaronmcové 1720, 756 61 Rozcaronnov p/R, Czech Republic;(2) LIP6 Laboratory, 4 Place Jussieu, 75252 Paris Cedex 05, France
Abstract:This paper details our allocation for Built-in Self Test (BIST) technique used by the core part of our Testability Allocation and Control System (TACOS) called IDAT. IDAT tool objective is to fulfill the designer requirements regarding selected design and testability attributes of a circuit data-path to be synthesized. A related tool is used to synthesize a test controller for the final testable circuit. The allocation process of BIST resources in the data-path is driven by two trade-off techniques performed in order to: (1) at the local level, select the optimal set of Functional Units (FUs) to be BISTed, using a new testability analysis method and (2) at the global level, for each selected FU of this set, choose either to allocate its BIST version (when available in a library) or to connect it to an internal Test Pattern Generator (TPG) and Test Results Checker (TRC). When necessary, a last step of the process is the allocation of scan chains used to test the remaining untested interconnections. Experiments show the results of our allocation for BIST technique on three benchmarks.
Keywords:BIST  synthesis for testability  DFT reuse  testability analysis
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