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Fast two's complement VLSI adder design |
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| Authors: | Dobson J.M. Blair G.M. |
| Affiliation: | Dept. of Electr. Eng., Edinburgh Univ.; |
| Abstract: | The design by Srinivas and Parhi (1992) which used redundant-number adders for fast two's complement addition is re-examined. The underlying mechanism is revealed and improvements are presented which lead to a static-logic binary-tree carry generator to support high speed adder implementations with a delay of [log2(N)]+2 gates |
| Keywords: | |