基于泰勒级数展开信号分辨算法的FPGA设计与实现

为了从硬件实现角度研究信号检测与分辨算法，提出了基于泰勒级数展开信号分辨算法的FPGA设计方案。在分析算法在理想脉冲情况下性能的基础上，针对扩频信号情况提出相应的改进，然后给出具体FPGA实现，结合静态时序分析进一步优化。最后通过仿真与上板实测，验证了该方案的可行性，算法最高可跑在150MHz频率下，具有良好的速度性能。实验结果表明，该方案满足设计需求，为其他算法的硬件实现提供了参考。

FPGA Design and Implementation of Taylor Series Expansion Based Signal Resolution Algorithm

In order to research signal detection and resolution algorithm from the perspective of hardware implementation, A FPGA design scheme based on Taylor series expansion based signal resolution algorithm is proposed. Based on the analysis of the performance of the algorithm in the case of ideal impulse, aiming at the situation of spread spectrum signal, a corresponding improvement is put forward. Then, a specific FPGA implementation is given, which is further optimized with static timing analysis. At last, the feasibility of this scheme is verified by simulation and on board test. The algorithm can run at a maximum frequency of 150MHz and has good speed performance. Experimental results show that the scheme meets the design requirements and provides a reference for the hardware implementation of other algorithms.