基于FPGA的LVDS传输链路的可靠性设计

在遥测系统中，LVDS接口作为许多采编、存储、测试台等设备的通信接口，有着传输速度高的优点，如果想保证数据传输的高效性与稳定性，必须确保LVDS传输链路的可靠性。在此次设计中，通过在硬件电路中增加阻抗匹配和均衡加重技术来提高电路的可靠性。在逻辑设计中，通过采用bit9和bit8标志位来区分有、无效数据与3路数字信号的方法来消除失锁现象，从而提高数据传输的稳定性。经过此方案设计，系统实现了以300Mbps/S的速率在30米屏蔽电缆中传输数据，误码率为零，提高了LVDS传输链路的可靠性与稳定性。

Based on the FPGA of an LVDS transmission link reliability design

In the telemetry system, an LVDS interface as many purchasing& cataloguing, storage, test bed equipment such as communication interface, has the advantage of high transmission speed, if you want to ensure the efficiency and stability of data transmission, must ensure the reliability of an LVDS transmission link. In this design, the reliability of the circuit is improved by increasing the impedance matching and the balanced weighting technology in the hardware circuit. In the logical design, the stability of data transmission is improved by using bit9 and bit8 marker bits to distinguish between the invalid data and the 3-way digital signal. Through this scheme design, the system realizes the transmission data of 300Mbps/S at 30 meters of shielding cable, the error rate is zero, and the reliability and stability of LVDS transmission link are improved.