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一种具有相位噪声跟踪补偿的全数字锁相环频率合成器
引用本文:梁珍珍,曹玉梅,赵海军. 一种具有相位噪声跟踪补偿的全数字锁相环频率合成器[J]. 电子器件, 2018, 41(1)
作者姓名:梁珍珍  曹玉梅  赵海军
摘    要:为了实现频率合成器中的相位噪声跟踪补偿和降低全数字锁相环的复杂性,本文提出了一种新的基于全数字锁相环的频率合成器。它采用了一种低复杂度的数字鉴频鉴相器和非线性相位/频率判决电路以及数控振荡器,从而显著降低了硬件复杂性。同时结构中采用的非线性相位和频率判决电路能够很好地实现噪声跟踪和快速的相位/频率捕获,数控振荡器能够获得高的频率分辨率(大约6kHz)和大的线性频率调谐范围。通过采用90nm CMOS工艺制造的ADPLL实验结果表明,本文所提出的基于全数字锁相环的频率合成器能够实现从100kHz到6MHz的可控环路带宽和相当好的带内相位噪声跟踪性能。

关 键 词:数字锁相环   复杂度   相位噪声跟踪   频率分辨率   频率合成

All Digital Phase-Locked Loop Based Frequency Synthesizer With Phase Noise Tracking Compensation
Abstract:A new frequency synthesizer based on all digital phase-locked loop is proposed in this paper to realize the phase noise tracking compensation and reduce the complexity of the all digital phase-locked loop. It uses an digital phase-frequency detector and a nonlinear phase/frequency decision circuit as well as a digitally-controlled oscillator with a low complexity, which significantly reduces the hardware complexity. At the same time,the proposed architecture is implemented in which the nonlinear phase and frequency the decision circuit can achieve good noise tracking and fast phase/ frequency acquisition and the digitally-controlled oscillator can achieve high frequency resolution (approximately 6kHz) and large linear frequency tuning range. The experimental results for ADPLL fabricated in CMOS 90nm technology show that the proposed frequency synthesizer based on all digital phase-locked loop can achieve a programmable loop bandwidth from 100kHz to 6MHz and an excellent in-band phase noise tracking performance.
Keywords:Digital phase-locked loop   Complexity   Phase noise tracking   Frequency resolution   Frequency synthesis
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