Characteristics of body-tied triple-gate pMOSFETs |
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Authors: | Tai-Su Park Hye Jin Cho Jeong Dong Choe Il Hwan Cho Donggun Park Yoon E Jong Ho Lee |
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Affiliation: | Sch. of Mater. Sci. & Eng., Seoul Nat. Univ., South Korea; |
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Abstract: | Body-tied triple-gate pMOSFETs were fabricated using bulk Si wafers and characterized. Process steps to implement the devices are explained briefly. Device characteristics of the triple-gate pMOSFETs were compared with those of the conventional planar channel device. While maintaining low off-leakage currents and threshold voltages similar to those of planar pMOSFETs in the parallel arrayed 30 000 transistors, the body-tied triple-gate MOSFETs showed about 74 mV/dec of subthreshold swing (92 mV/dec for conventional devices) and a drain-induced barrier lowering of 34 mV/V (92 mV/V for conventional devices). It was also addressed that I/sub SUB//I/sub D/ of the body-tied triple-gate is lower than that of the planar channel device. |
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