FPGA教学中时序概念的教学与实验设计

本文针对FPGA教学和程序设计中较难理解的时序问题,阐述了PLD电路设计中时序的相关概念并设计了相应的教学实验。本文在调研PLD教学现状的基础上,归类整理了与PLD设计中与时序相关的基本概念,并依托一个"4比特计数器时序分析"的基础实验设计,加深学生对这些概念的认识和理解。

Design of Theoretical and Experimental Teaching on FPGA Timing

In order to help the students better understanding the concepts of FPGA timing,the relevant concepts of timing in PLD circuit is discussed together with the appropriate experiments. The investigation of the available status of PLD teaching is introduced first. Then this paper made a classification of several basic concepts on Timing related to the PLD design. At last,a fundamental experiment to explore the FPGA timing by a 4-bit counter design experiment is presented,which can deepen students＇ understanding of these concepts.