| 基于FPGA的CIC抽取滤波器设计与实现 |
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| 引用本文： | 雷能芳.基于FPGA的CIC抽取滤波器设计与实现[J].计算机与数字工程,2012,40(1):137-139. |
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| 作者姓名： | 雷能芳 |
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| 作者单位： | 渭南师范学院物理与电气工程学院 渭南714000 |
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| 基金项目： | 陕西省军民融合研究基金项目（编号：11JMR07）资助 |
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| 摘 要： | 现场可编程门阵列（FPGA）器件广泛应用于数字信号处理领域,而使用VHDL或Verilog HDL语言进行设计比较复杂。针对软件无线电中的多速率信号处理技术,提出了一种采用DSP Builder实现级联积分梳状（CIC）抽取滤波器的FPGA实现方案。软件仿真和硬件测试验证了设计的正确性和可行性。
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| 关 键 词： | 级联积分梳状滤波器 抽取 现场可编程门阵列 DSPBuilder |
Design and Implementation of CIC Decimation Filter Based on FPGA |
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| LEI Nengfang.Design and Implementation of CIC Decimation Filter Based on FPGA[J].Computer and Digital Engineering,2012,40(1):137-139. |
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| Authors: | LEI Nengfang |
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| Affiliation: | LEI Nengfang(School of Physics and Electrical Engineering,Weinan Teachers University,Weinan 714000) |
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| Abstract: | Field Programmable Gate Array（FPGA） devices is widely used in the field of digital signal processing,but it is complicated to design using VHDL or Verilog HDL.For the multi-rate signal processing technology in software radio,this paper porposed a scheme for implementation of Cascade Integrator Comb decimation filter based on FPGA and DSP Builder.The correctness and feasibility of the design is verified by software simulation and hardware test. |
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| Keywords: | CIC filter decimation FPGA DSP Builder |
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