Transistor network restructuring against NBTI degradation |
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| Authors: | Paulo F. Butzen Vinícius Dal Bem André I. Reis Renato P. Ribas |
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| Affiliation: | 1. Department of Electronics Engineering, Shanghai Key Laboratory of Multidimensional Information Processing, East China Normal University, Shanghai, China;2. Shanghai Integrated Circuit Research & Development Center, Shanghai, China;1. Instituto de Informática, PPGC/PGMICRO, Universidade do Rio Grande do Sul (UFRGS), Porto Alegre, Brazil;2. Departamento de Informática e Estatística, Universidade Federal de Santa Catarina (UFSC), Florianópolis, Brazil;3. ONERA/DPHY, Université de Toulouse, F-31055 Toulouse, France;2. Université de Montpellier;3. Federal University of Rio Grande do Sul |
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| Abstract: | Negative Bias Temperature Instability (NBTI) has become a critical reliability concern for nanometer PMOS transistors. A logic function can be designed by alternative transistor networks. This work evaluates the impact of the NBTI effect in the delay of CMOS gates considering both the effect of intra-cell pull-up structures and the effect of decomposing the function into multiple stages. Intra-cell pull-up PMOS transistor arrangements have been restructured to minimize the number of devices under severe NBTI degradation. Also, circuits decomposed into more than one stage have been compared to their single stage design version. Electrical simulation results reveal that the restructuring of intra-cell transistor networks recovers up to 15% of rise delay degradation due to NBTI, while the decomposition of single stage circuit topologies into multi-stage topologies tends to reduce the rise degradation delay at a cost of fall delay degradation. |
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