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Threshold voltage instabilities in p-channel power VDMOSFETs under pulsed NBT stress
Authors:N. Stojadinović  D. Danković  I. Manić  A. Prijić  V. Davidović  S. Djorić-Veljković  S. Golubović  Z. Prijić
Affiliation:1. Faculty of Electronic Engineering, University of Ni?, A. Medvedeva 14, 18000 Ni?, Serbia;2. Faculty of Civil Engineering and Architecture, University of Ni?, A. Medvedeva 14, 18000 Ni?, Serbia;1. Department of Electronics and Communication, Government Engineering College Ajmer, India;2. Department of Physics, SD(PG) College, Muzaffarnagar (C.C.S. University), India;3. Department of Electronics and Communication, University of Allahabad, 211002, India;1. Department of Industrial Engineering, University of Catania, Viale A. Doria, 6, 95125 Catania, Italy;2. Department of Chemistry, University “Sapienza” of Rome, P.le A. Moro 5, 00185 Rome, Italy;1. Department of Information Technology, College Of Engineering & Management, Kolaghat, India;2. Department of Computer science & Engineering, College Of Engineering & Management, Kolaghat, KTPP Township, Purba Medinipur 721171, West Bengal, India;3. Mechanical Operation (stage-II), Kolaghat Thermal Power Station, WBPDCL, Purba Medinipur 721137, West Bengal, India;1. Materials Center Leoben Forschung GmbH, Roseggerstrasse 12, 8700 Leoben, Austria;2. Institut für Struktur- und Funktionskeramik, Montanuniversitaet Leoben, Peter-Tunner-Strasse 5, 8700 Leoben, Austria;3. Institut für Mechanik, Montanuniversitaet Leoben, Franz-Josef-Strasse 18, 8700 Leoben, Austria;4. AT&S AG, Fabriksgasse 13, 8700 Leoben, Austria;5. Thales Global Services, 18, avenue du Maréchal Juin, 92360 Meudon-la-Forêt, France;1. Facultad de Ingeniería, INIQUI (CONICET), Universidad Nacional de Salta, Av. Bolivia 5150, 4400 Salta, Argentina;2. CIMNE International Center for Numerical Method Engineering, Spain;3. UPC, Technical University of Catalonia (Barcelona Tech), Edif. C1, Campus Nord, Jordi Girona 1–3, 08034 Barcelona, Spain
Abstract:Threshold voltage instabilities induced in p-channel power VDMOSFETs by pulsed negative bias temperature stressing are presented and compared with corresponding instabilities found after the static NBT stress. Degradation observed under the pulsed stress conditions depends on the frequency and duty cycle of stress voltage pulses, and is generally lower than the one found after the static NBT stress. Optimal frequency and duty cycle ranges for application of investigated devices are proposed as well. By selecting an appropriate combination of frequency range (1 kHz < f < 5 kHz) and duty cycle (about 25%), the pulsed stress-induced ΔVT can be reduced to a quarter of ΔVT found after the static NBT stress.
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