| 一种大数模幂的硬件实现设计 |
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| 引用本文： | 王晓林,周玉洁. 一种大数模幂的硬件实现设计[J]. 信息技术, 2005, 29(10): 41-44 |
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| 作者姓名： | 王晓林 周玉洁 |
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| 作者单位： | 上海交通大学信息安全学院通信与信息系统专业,上海,200030 |
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| 摘 要： | 提出了一种实现大数模幂的硬件设计方法。其中的大数模乘部分基于基2的Montgomery改进算法，采用模乘心动阵列结构，提出了一种双边沿触发串行计算的新结构，节约了面积，同时可以达到较高的时钟频率。模幂部分基于M-ary算法，减少了所需模乘运算的次数。并比较了这种实现方法与常见的L-R二进制幂算法的实现方式速度上的改进。
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| 关 键 词： | 模幂 Mongomery模乘 M—ary算法 |
| 文章编号： | 1009-2552(2005)10-0041-03 |
| 修稿时间： | 2005-05-12 |
A hardware design for modular exponentiation of big number |
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| WANG Xiao-lin,ZHOU Yu-jie. A hardware design for modular exponentiation of big number[J]. Information Technology, 2005, 29(10): 41-44 |
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| Authors: | WANG Xiao-lin ZHOU Yu-jie |
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| Abstract: | This paper presents a hardware design for modular exponentiation of big number,in which modular multiplication is based on the modified Montgomery arithmetic(radix-2).It adopts a systolic modular multiplication structure and brings forward a new serial structure trigger at dual-edge of clock,which can save (area) and achieve high clock frequency at the same time.The modular exponentiation part of the design is based on the M-ary arithmetic,which can save times of calculation.Also it has compared the speed with that of the design based on the common used L-R arithmetic. |
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| Keywords: | Modular exponentiation Montgomery modular multiplication M-ary arithmetic |
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