Power Consumption of Quasi-adiabatic Logic Gates

A computer simulation is carried out to investigate the power consumption of major quasi-adiabatic logic gates. Anomalously high dissipation is found at low clock rates. An explanation for the anomaly and a method of eliminating this are proposed. For the dissipated energy W and the clock rate f, it is found that W fC^{1 +} as f tends to infinity, where is essentially less than unity. The mechanism of the phenomenon is identified. Rules are established that govern the power consumption of the logic gates. It is concluded that they should help one to strike a balance between power consumption and speed, to optimize power characteristics, and to predict the performance of future models made by better process technologies.