The electrical and interface properties of metal-ferroelectric (lanthanum substituted bismuth titanate: BLT)-insulator-semiconductor (MFIS) structures with various insulators

We have investigated metal-ferroelectric-insulator semiconductor (MFIS) structures with lanthanum substituted bismuth titanate (BLT) as a ferroelectric layer and lanthanum oxide (LO) or zirconium silicate (ZSO) as an insulating buffer layer between BLT and Si substrate. The morphology of BLT films deposited on LO or ZSO oxide was not changed due to the good thermal stability of LO and ZSO films. But an interface reaction between BLT and buffer layer started at high annealing temperature (750 °C), which was confirmed by transmission electron microscopy (TEM) and energy dispersive X-ray spectroscopy (EDS). The maximum memory window was 3.59 V at a sweep voltage of 7 V with the LO film annealed at 650 °C and a thickness of 5 nm. With BLT/LO annealed at 750 °C, the window was decreased due to the reaction between the BLT film and LO. The memory window was about 1 V lower with a ZSO film because ZSO film has a lower dielectric constant than LO film. The MFIS structure annealed at 750 °C had a lower leakage current density because the electrical properties of the buffer layer (La oxide or Zr silicate) were improved by the thermal process.