一种适用于内嵌时钟串行链路的5Gbps小面积CDR

本文提出了一种支持多标准的具有系数可调的均衡器和宽跟踪能力的时钟数据恢复电路。基于对系统参数和一阶 bang-bang 时钟数据恢复电路的环路特性分析,推导出电路设计参数。考虑到抖动性能,追踪能力以及芯片面积,文中采用了一阶数字滤波器和6-bit DAC以及高线性度的相位插值器实现了高相位调整精度和小面积的时钟恢复电路,同时该结构实现了±2200ppm的频偏跟踪能力,使得该结构适用于不同源的高速串行传输系统,尤其是内嵌时钟结构。该设计已经在55nm CMOS工艺上流片验证,测试结果显示符合误码率的要求以及抖动容忍规范。该测试芯片整体面积是0.19mm2,其中时钟恢复电路只占0.0486mm2 而且该电路工作在5Gbps,供电电压为1.2V时,只消耗30mW。

A 5 Gb/s low area CDR for embedded clock serial links

A multi-standard compatible clock and data recovery circuit (CDR) with a programmable equalizer and wide tracking range is presented. Considering the jitter performance, tracking range and chip area, the CDR employs a first-order digital loop filter, two 6-bit DACs and high linearity phase interpolators to achieve high phase resolution and low area. Meanwhile the tracking range is greater than ± 2200 ppm, making this proposed CDR suitable for the embedded clock serial links. A test chip was fabricated in the 55 nm CMOS process. The measurements show that the test chip can achieve BER < 10^-12 and meet the jitter tolerance specification. The test chip occupies 0.19 mm² with a 0.0486 mm² CDR core, which only consumes 30 mW from a 1.2 V supply at 5 Gb/s.