Reconfigurable Architecture for Deinterlacer based on Algorithm/Architecture Co-Design |
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Authors: | Gwo Giun Lee Ming-Jiun Wang Bo-Han Chen JiunFu Chen Ping-Keng Jao Ching Jui Hsiao Ling-Fei Wei |
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Affiliation: | (1) Media SoC Lab., Department of Electrical Engineering, National Cheng Kung University, No.1, Ta-Hsueh Road, Tainan, 701 Taiwan, R.O.C.; |
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Abstract: | This paper presents the algorithm and reconfigurable architecture of motion-adaptive deinterlacer for high-definition video.
The content-adaptability of algorithm and the reconfiguration of architecture are concurrently explored by algorithm/architecture
co-design methodology and Caltrop actor language (CAL) modeling of the dataflow. In the design methodology we employed, the
CAL dataflow model is also very helpful in the verification of our deinerlacer. The proposed algorithm and architecture design
of deinterlacer is more cost-efficient than two recently proposed works in terms of algorithmic performance and silicon area
of VLSI implementation. Moreover, data path reconfiguration efficiently enables various interpolation schemes using less computational
resource of hardware than non-reconfigurable architecture. |
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