Power aware channel width tapering of serially connected MOSFETs

This paper reviews a transistor channel width tapering scheme called Hill Tapering for FET chains with specific emphasis on power dissipation and layout area of the tapered chains. The Hill Tapering scheme results in the lowest power dissipation and physical area compared to any of the existing tapering schemes like linear, exponential or optimal tapering. It also offers high speed operation. This tapering scheme is general and suits domino logic circuit designs. SPICE simulation results have shown that up to 81% power dissipation reduction could be achieved by using this tapering scheme.