Efficient implementation of modular multiplication over 192-bit NIST prime for 8-bit AVR-based sensor node |
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Authors: | Park Dong-won Hong Seokhie Chang Nam Su Cho Sung Min |
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Affiliation: | 1.Center for Information Security Technologies (CIST), Korea University, Seoul, 02841, South Korea ;2.Sejong Cyber University, Seoul, 05000, South Korea ;3.Crypt & Tech, Seoul, 02841, South Korea ; |
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Abstract: | Modular multiplication is one of the most time-consuming operations that account for almost 80% of computational overhead in a scalar multiplication in elliptic curve cryptography. In this paper, we present a new speed record for modular multiplication over 192-bit NIST prime P-192 on 8-bit AVR ATmega microcontrollers.
We propose a new integer representation named Range Shifted Representation (RSR) which enables an efficient merging of the reduction operation into the subtractive Karatsuba multiplication. This merging results in a dramatic optimization in the intermediate accumulation of modular multiplication by reducing a significant amount of unnecessary memory access as well as the number of addition operations. Our merged modular multiplication on RSR is designed to have two duplicated groups of 96-bit intermediate values during accumulation. Hence, only one accumulation of the group is required and the result can be used twice.
Consequently, we significantly reduce the number of load/store instructions which are known to be one of the most time-consuming operations for modular multiplication on constrained devices. Our implementation requires only 2888 cycles for the modular multiplication of 192-bit integers and outperforms the previous best result for modular multiplication over P-192 by a factor of 17%. In addition, our modular multiplication is even faster than the Karatsuba multiplication (without reduction) which achieved a speed record for multiplication on AVR processor. |
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