A 12.5-ns 16-Mb CMOS SRAM with common-centroid-geometry-layoutsense amplifiers |
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| Authors: | Ishibashi K Komiyaji K Morita S Aoto T Ikeda S Asayama K Koike A Yamanaka T Hashimoto N Iida H Kojima F Motohashi K Sasaki K |
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| Affiliation: | Central Res. Lab., Hitachi Ltd, Tokyo; |
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| Abstract: | A 16-Mb CMOS SRAM using 0.4-μm CMOS technology has been developed. This SRAM features common-centroid-geometry (CCG) layout sense amplifiers which shorten the access time by 2.4 ns. A flexible redundancy technique achieves high efficiency without any access penalty. A memory cell with stacked capacitors is fabricated for high soft-error immunity. A 16-Mb SRAM with a chip size of 215 mm2 is fabricated and an address access time of 12.5 ns has been achieved |
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