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Double-gate 1T-DRAM cell using nonvolatile memory function for improved performance |
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| Authors: | Ki-Heung Park Sorin Cristoloveanu Maryline Bawedin Youngho Bae Kyoung-Il Na Jong-Ho Lee |
| Affiliation: | a Foundry Business Team, Samsung Electronics Co., Ltd. San #24, Nongseo, Giheung, Yongin, Kyunggi-Do 446-711, Republic of Korea;b Institute of Microelectronics, Electromagnetism and Photonics (IMEP-LAHC, UMR 5130), Grenoble Polytechnic Institute, MINATEC, B.P. 257, 38016 Grenoble Cedex 1, France;c Department of Electronics Engineering, Uiduk University, Gyeongju 780-713, Republic of Korea;d School of EECS Eng. and ISRC (Inter-University Research Center), Seoul National University, Gwanak P.O. Box 34, Seoul 151-600, Republic of Korea |
| Abstract: | We propose a double-gate (DG) 1T-DRAM cell combining SONOS type storage node on the back-gate (control-gate) for nonvolatile memory function. The cell sensing margin and retention time characteristics were systematically examined in terms of control-gate voltage (Vcg) and nonvolatile memory (NVM) function. The additional NVM function is achieved by Fowler-Nordheim (FN) tunneling electron injection into the nitride storage node. The injected electrons induce a permanent hole accumulation layer in silicon body which improves the sensing margin and retention time characteristics. To demonstrate the effect of stored electrons in the nitride layer, experimental data are provided using 0.6 μm devices fabricated on SOI wafers. |
| Keywords: | 1T-DRAM DRAM Double-gate (DG) MOSFET Nonvolatile memory Floating-body effect Silicon-on-insulator (SOI) MOSFETs |
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