Reliability of pFET EEPROM with 70-/spl Aring/ tunnel oxide manufactured in generic logic CMOS Processes |
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Authors: | Yanjun Ma Gilliland T Bin Wang Paulsen R Pesavento A Wang C-H Hoc Nguyen Humes T Diorio C |
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Affiliation: | Impinj Inc., Seattle, WA, USA; |
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Abstract: | We investigate the reliability of pFET-based EEPROMs with 70-/spl Aring/ tunneling oxides fabricated in standard foundry 0.35-/spl mu/m, 0.25-/spl mu/m, and 0.18-/spl mu/m logic CMOS processes. The floating-gate memory cell uses Fowler-Nordheim tunneling erase and impact-ionization generated hot-electron injection for programming. We show that charge leakage is dominated by the leakage through interlayer dielectrics. We propose a retention model and show the data retention lifetime exceeds 10 years. These results demonstrate the feasibility of producing nonvolatile memory using standard logic processes that have a 70-/spl Aring/ oxide. |
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