A simple method for modeling VLSI yields

Data show that simplistic models of yield as a function of chip area are not realistic. Yield of ROS ($\text{R}$ead $\text{O}$nly $\text{S}$tore) chips as a function of the number of bits results, however, in a smooth relationship. This observation appeared to hold for three manufacturing lines. The authors therefore propose that yields should be modeled by the number of circuits rather than by chip area.