Gzip压缩的硬件加速电路设计

硬件无损压缩技术可以发挥专用电路的速度和功耗优势，被广泛应用于大数据计算以及通信领域.本文以GNUzip（Gzip）数据无损压缩技术为原型设计了一种硬件压缩电路.通过采用双Hash函数、并行匹配处理、面向硬件存储的LZ77压缩存储格式、高效数据拼接器等加速方法，发挥并行计算和流水线结构优势，提升压缩速率.该硬件压缩电路基于Verilog HDL设计，使用现场可编程门阵列（FPGA）进行测试和验证.测试数据表明：与软件压缩方式相比，该硬件压缩电路在获得适中压缩率（65.9%）的同时，其压缩速率得到显著提升，平均压缩速率达171Mb/s，满足网络通信、数据存储等实时压缩应用需求.

Hardware-Accelerated Circuit Design for Gzip Compression

The hardware implementation of lossless data compression is wildly used in big data computing and communication,since it combines the speed and power advantage of the dedicated circuit.This paper proposed a hardware compression circuit based on GNUzip(Gzip) lossless data compression algorithm.The dual Hash functions,parallel match processing,hardware storage oriented LZ77 compression data format and high-performance data adaptor were involved to accelerate the compression speed with the advantages of parallel calculation and pipeline structure.The hardware compression circuit,based on Verilog HDL,was tested and verified by field programmable gate array (FPGA).The test data shows that,compared with software implementation,the compression speed of hardware circuit is improved significantly while the compression rate is 65.9％.The average speed is up to 171Mb/s that can satisfy the real-time compression requests of network communication and data storage.