一个用于背板通信的24Gb/s高速自适应组合均衡器

本文介绍了应用于背板通信系统中均衡器的设计与实现.该均衡器采用连续时间线性均衡器（Continuous Time Linear Equalizer，CTLE）和2抽头判决反馈均衡器（Decision Feedback Equalizer，DFE）的组合结构来消除信道码间干扰中的前标分量和后标分量.在设计中，CTLE采用双路均衡器结构补偿信道不同频率的损耗，减小了电路的面积和功耗；DFE采用半速率预处理结构来缓解传统DFE结构中关键反馈路径的时序限制，并采用模拟最小均方（Least Mean Square，LMS）算法电路控制DFE系数的自适应.电路采用IBM 0.13μm BiCMOS工艺设计并实现，测试结果表明对于经过18英寸背板后眼图完全闭合的24Gb/s的信号，均衡后的眼图水平张开度达到了0.81UI.整个均衡器芯片包括焊盘在内的芯片面积为0.78×0.8mm²，在3.3V的电源电压下，功耗为624mW.

A 24Gb/s High Speed Adaptive Combined Equalizer for Backplane Communication

This paper introduces the design and implementation of equalizer in the backplane communication system.The equalizer uses a combination of continuous time linear equalizer (CTLE) and 2 tap decision feedback equalizer (DFE) to cancel both pre-cursor and post-cursors ISI.In the design,CTLE compensates with different frequencies of the loss of the channel by employing split-path equalizer,reduced the circuit area and power consumption.A half-rate speculative architecture is adopted to improve the transmitted data rate in DFE by relaxing the timing constraint on the first feedback path.An analog implementation of the LMS algorithm is used to control the DFE tap coefficients.Circuit using IBM 0.13μm BiCMOS process design and implement.Measured results show that the eye is completely closed when 24Gb/s signal through 18 inches backplane,the horizontal opening degree of equalized eye reached 0.81UI.The entire equalizer chip area including pads is 0.78×0.8mm2,and consumes 624mW with the supply voltage of 3.3V.