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A 30-ns 64-Mb DRAM with built-in self-test and self-repair function |
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| Authors: | Tanabe A Takeshima T Koike H Aimoto Y Takada M Ishijima T Kasai N Hada H Shibahara K Kunio T Tanigawa T Saeki T Sakao M Miyamoto H Nozue H Ohya S Murotani T Koyama K Okuda T |
| Affiliation: | NEC Corp., Kanagawa; |
| Abstract: | A 64-Mb dynamic random access memory (DRAM) with a 30-ns access time and 19.48-mm×9.55-mm die size has been developed. For reducing inter-bit-line coupling noise, the DRAM features a latched-sense, shared-sense circuit with open bit-line readout and folded bit-line rewrite operations. To reduce test costs and increase chip reliability, it has been equipped with built-in self-test and self-repair (BIST and BISR) circuits that use spare SRAM cells |
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