| 一种应用于流水线ADC的14-bit 50MS/s 采样保持电路 |
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| 引用本文： | 岳森,赵毅强,庞瑞龙,盛云. 一种应用于流水线ADC的14-bit 50MS/s 采样保持电路[J]. 半导体学报, 2014, 35(5): 055009-6 |
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| 作者姓名： | 岳森 赵毅强 庞瑞龙 盛云 |
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| 作者单位： | School of Electronic Information Engineering, Tianjin University |
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| 摘 要： | A high performance sample-and-hold （S/H） circuit used in a pipelined analog-to-digital converter （ADC） is presented. Capacitor flip-around architecture is used in this S/H circuit with a novel gain-boosted differential folded cascode operational transconductance amplifier. A double-bootstrapped switch is designed to improve the performance of the circuit. The circuit is implemented using a 0.18 μm 1P6M CMOS process. Measurement results show that the effective number of bits is 14.03 bits, the spurious free dynamic range is 94.62 dB, the signal to noise and distortion ratio is 86.28 dB, and the total harmonic distortion is -91.84 dB for a 5 MHz input signal with 50 MS/s sampling rate. A pipeline ADC with the designed S/H circuit has been implemented.
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| 关 键 词： | 保持电路 ADC 流水线 采样率 MS 运算跨导放大器 总谐波失真 折叠共源共栅 |
A 14-bit 50 MS/s sample-and-hold circuit for pipelined ADC |
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| Yue Sen,Zhao Yiqiang,Pang Ruilong and Sheng Yun. A 14-bit 50 MS/s sample-and-hold circuit for pipelined ADC[J]. Chinese Journal of Semiconductors, 2014, 35(5): 055009-6 |
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| Authors: | Yue Sen Zhao Yiqiang Pang Ruilong Sheng Yun |
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| Affiliation: | School of Electronic Information Engineering, Tianjin University, Tianjin 300072, China;School of Electronic Information Engineering, Tianjin University, Tianjin 300072, China;School of Electronic Information Engineering, Tianjin University, Tianjin 300072, China;School of Electronic Information Engineering, Tianjin University, Tianjin 300072, China |
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| Abstract: | sample/hold circuit pipeline ADC gain-boosted OTA bootstrapped switch |
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| Keywords: | sample/hold circuit pipeline ADC gain-boosted OTA bootstrapped switch |
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