A byte organized NMOS/CCD memory with dynamic refresh logic

A 9216 bit NMOS/CCD memory organized as 1024 words by 9 bits is described. It employs a buried channel two phase charge-coupled device (CCD) storage cell combined with n-channel silicon gate Isoplanar (TM) MOS technology for logic functions and TTL compatible interfacing. Techniques of charge detection by using internally generated reference voltages are detailed. A low noise CCD input writing scheme and a dynamic sense-refresh cell are described. Input-output logic is given that permits operating modes of read, write, read-modify-write, and recirculate. Operation at the specification limits of 100 kHz and 2 MHz is shown.