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An efficient memory control method for video and image processing in digital TV |
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| Affiliation: | 1. Electronics and Computer Science, University of Southampton, Southampton SO17 1BJ, UK;2. School of Systems Engineering, University of Reading, Reading RG6 6AY, UK;3. Electrical and Computer Engineering Department, Faculty of Engineering, King Abdulaziz University, Jeddah 21589, Saudi Arabia;1. Department of Information Management, National University of Kaohsiung, 700, Kaohsiung University Rd., Nanzih District, 81148 Kaohsiung, Taiwan, ROC;2. Department of Information Management, Kun Shan University, 195, Kunda Rd., YongKang District, 71070 Tainan, Taiwan, ROC;3. Department of Information Management, I-Shou University, No. 1, Sec. 1, Syuecheng Rd., Dashu District, Kaohsiung City 84001, Taiwan, ROC;1. Division of Cardiology, Department of Medicine, Columbia University Medical Center, New York, United States;2. Department of Pharmacology, Columbia University Medical Center, New York, United States;3. Division of Cardiovascular Diseases & Hypertension, Rutgers Robert Wood Johnson Medical School, New Brunswick, NJ, United States;4. Myocardial Function Section, Imperial College and Imperial NHS Trust, London, United Kingdom |
| Abstract: | High definition (HD) and ultra-high definition (UHD) digital TV require high-resolution images and lots of data transfers between processors and memory devices often become the bottleneck of the system. Video and image signal processing usually require blocks of square or rectangular shaped pixel data for signal processing. It requires frequent precharging and activating new rows, and results in extra latencies for reading and writing pixel data in memory devices. This paper proposes an efficient memory controller for video and image processing to reduce the latencies for reading and writing blocks of pixel data. The controller stores a frame of pixel data by distributing contiguous lines of pixel data to multiple banks in sequence. Its efficiency is enhanced more with an interface protocol such as AMBA AXI in which outstanding transactions are allowed. Memory controllers according to the proposed scheme are designed and the performance and the efficiency are compared with the previous works. |
| Keywords: | Memory controller Image signal processing Address generation SDRAM |
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