CMOS realization of two-dimensional mixed analog-digital Hamming distance discriminator circuits for real-time imaging applications |
| |
Authors: | Sté phane Badel,Yusuf Leblebici |
| |
Affiliation: | Microelectronic Systems Laboratory LSM, Swiss Federal Institute of Technology EPFL, CH-1015 Lausanne, Switzerland |
| |
Abstract: | The architecture of an integrated Hamming artificial neural network, and its use as a versatile signal/image processing circuit is presented. The circuit operation relies on the charge-based processing of sum-of-products terms, complemented with digital post-processing. The synthesis of complex functions such as winner-(loser)-take-all, k-winner-(loser)-take-all, rank ordering are demonstrated with a minimal hardware overhead. Different operation modes and corresponding hardware configurations are presented. The VLSI realization of the core two-dimensional Hamming distance discriminator, and the chip measurements are discussed. As such, the presented Hamming discriminator is uniquely suitable for real-time image processing and alignment applications. |
| |
Keywords: | Hamming artificial neural network Image processing hardware |
本文献已被 ScienceDirect 等数据库收录! |
|