H.264指数哥伦布码解码部件的硬件设计和实现

提出了一种针对H.264视频编码标准的变长码-指数哥伦布码解码的硬件设计结构,对传统的桶形移位器进行优化,主要采用基于PLA的并行解码算法以达到实时解码,同时辅助使用串行解码算法降低硬件资源消耗,保证在能够对符合H.264标准baseline Profile的码流实时解码的基础上优化了电路资源,给出实现该硬件结构对应的FPGA仿真结果及其ASIC硬件规模.

DVB-RCS Technology for Satellite Interactive Communication

This paper presents the hardware design of a decoder for H.264 Variable-Length code named Exp-Golomb code. This design optimizes the traditional barrel shifter and uses the parallel decode algorithm based on PLA mainly to realize the real-time decoding. At the same time, the serial decode algorithm is used to reduce the hardware resource. This design is proved to be able to decode the real-time bitstream of H.264 baseline Profile. The hardware design is introduced in detail and finally the simulation result of FPGA and hardware scale of ASIC is offered in this paper.