| 一种高效率MCU芯片Multi-Sites测试技术 |
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| 引用本文： | 陈真,陆锋,张凯虹. 一种高效率MCU芯片Multi-Sites测试技术[J]. 电子与封装, 2014, 0(11): 13-15 |
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| 作者姓名： | 陈真 陆锋 张凯虹 |
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| 作者单位： | 1. 江南大学物联网工程学院，江苏无锡214122; 中国电子科技集团公司第58研究所，江苏无锡 214035
2. 中国电子科技集团公司第58研究所,江苏无锡,214035 |
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| 摘 要： | 介绍了使用Multi-Sites工程测试技术提高MCU芯片测试效率的方案。针对MCU芯片Multi-Sites测试难点,阐述了在MCU芯片Multi-Sites测试中电性能测试、功能测试的影响因素和解决方案,并对MCU芯片Multi-Sites测试过程中经常遇到的干扰因素进行分析,保证MCU芯片Multi-Sites测试获得稳定可靠的性能参数,有效提高测试效率。
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| 关 键 词： | MCU Multi-Sites 测试效率 |
A High Efifciency Multi-Sites Testing Technology for MCU Chip |
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| CHEN Zhen,LU Feng,ZHANG Kaihong. A High Efifciency Multi-Sites Testing Technology for MCU Chip[J]. Electronics & Packaging, 2014, 0(11): 13-15 |
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| Authors: | CHEN Zhen LU Feng ZHANG Kaihong |
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| Affiliation: | CHEN Zhen, LU Feng, ZHANG Kaihong ( 1. College of Internet of Thing, Jiangnan University, Wuxi 214122, China; 2. China Electronics Technology Group Corporation No.58 Research Institute, Wuxi 214035, China) |
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| Abstract: | Describes the use of multi-sites engineering testing technology to improve test MCU chip testing efficiency programs. For MCU chip multi-sites testing difficulties, elaborated factors and solutions for electrical performance testing, functional testing of the MCU chip multi-sites testing. And analyzing the interference factor MCU chip multi-sites testing process often encountered MCU chip to ensure stable and reliable test performance parameters, improve test efficiency. |
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| Keywords: | MCU multi-sites test efifciency |
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