256-Mb DRAM circuit technologies for file applications |
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| Authors: | Kitsukawa G Horiguchi M Kawajiri Y Kawahara T Akiba T Kawase Y Tachibana T Sakai T Aoki M Shukuri S Sagara K Nagai R Ohji Y Hasegawa N Yokoyama N Kisu T Yamashita H Kure T Nishida T |
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| Affiliation: | Central Res. Lab., Hitachi Ltd., Kokubunji; |
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| Abstract: | 256-Mb DRAM circuit technologies characterized by low power and high fabrication yield for file applications are described. The newly proposed and developed circuits are a self-reverse-biasing circuit for word drivers and decoders to suppress the subthreshold current to 3% of the conventional scheme, and a subarray-replacement redundancy technique that doubles chip yield and consequently reduces manufacturing costs. An experimental 256-Mb DRAM has been designed and fabricated by combining the proposed circuit techniques and a 0.25-μm phase-shift optical lithography, and its basic operations are verified. A 0.72-μm2 double-cylindrical recessed stacked-capacitor (RSTC) cell is used to ensure a storage capacitance of 25 fF/cell. A typical access time under a 2-V power supply voltage was 70 ns. With the proper device characteristics, the simulated performances of the 256-Mb DRAM operating with a 1.5-V power supply voltage are a data-retention current of 53 μA and an access time of 48 ns |
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