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| 基于锗硅工艺的40-Gb/s分接器 | |
| 引用本文： | 王贵,王志功,李伟,唐万春.基于锗硅工艺的40-Gb/s分接器[J].固体电子学研究与进展,2009,29(2). |
| 作者姓名： | 王贵 王志功 李伟 唐万春 |
| 作者单位： | 1. 南京理工大学,电子工程与光电技术学院,南京,210094;东南大学,射频与光电集成电路研究所,南京,210096 2. 东南大学,射频与光电集成电路研究所,南京,210096 3. 南京理工大学,电子工程与光电技术学院,南京,210094 |
| 基金项目： | 国家863计划项目支持 |
| 摘 要： | 采用0.35μmSiGeBiCMOS工艺设计了一个1∶2分接器,核心电路单元采用经过改进的电路结构实现。由于传统的发射极耦合逻辑结构(ECL)电路的工作速度不能达到要求,对此加以了改进,在发射极耦合逻辑结构中增加一级射极跟随器,形成发射极-发射极耦合逻辑(E2CL)结构,从而提高电路的工作速度。测试结果显示,所设计分接器的工作速度可以达到40Gb/s。整个电路采用单电源5V供电,功耗为510mW。 |
| 关 键 词： | 分接器 锗硅 锁存器 缓冲器 发射极-发射极耦合逻辑 |
40-Gb/s Demultiplexer Based on SiGe Process |
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| WANG Gui,WANG Zhigong,LI Wei,TANG Wanchun.40-Gb/s Demultiplexer Based on SiGe Process[J].Research & Progress of Solid State Electronics,2009,29(2). | |
| Authors: | WANG Gui WANG Zhigong LI Wei TANG Wanchun |
| Affiliation: | School of Electronic Engineering and Optoelectronic Technology;NUST;Nanjing;210094;CHN;Institute of RF-& OE-ICs;Southeast University;210096;CHN |
| Abstract: | A 1∶2 demultiplexer was designed in 0.35 μm SiGe BiCMOS process.An improved structure was used to realize the core cell of this circuit.The traditional emitter-coupled-logic(ECL)circuit can not satisfy the requirement.So in this paper,the emitter-emitter-coupled-logic(E2CL)improved by adding an emitter follower to ECL was used.This can increase its speed.The measurement results show that this demultiplexer can operate at the data rate of 40 Gb/s.The whole circuit with single 5 V supply consumes 510 mW. |
| Keywords: | demultiplexer SiGe latch buffer emitter-emitter coupled logic |
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