| 200V高压大电流VDMOS的研制 |
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| 引用本文： | 胡佳贤,韩雁,张世峰,张斌,宋波. 200V高压大电流VDMOS的研制[J]. 固体电子学研究与进展, 2011, 31(1): 85-89 |
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| 作者姓名： | 胡佳贤 韩雁 张世峰 张斌 宋波 |
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| 作者单位： | 浙江大学微电子与光电子研究所,杭州,310027 |
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| 基金项目： | 广东省省级财政支持技术项目 |
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| 摘 要： | 介绍了自主研制的200 V/40 A VDMOS晶体管的设计优化过程及研制结果.该器件采用JFET注入和浅P-body方法降低导通电阻,提高电流密度,采用优化的N掺杂硅外延材料优化导通电阻和击穿电压.测试结果表明击穿电压高于215 V,特征导通电阻1.2 Ω·mm2,导通电流可达40 A;同时设计了ESD防护,HBM值...
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| 关 键 词： | 垂直双扩散金属氧化物场效应晶体管 大电流 导通电阻 结型场效应区注入 静电防护 |
The Development of the 200 V VDMOS with Large Current |
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| HU Jiaxian,HAN Yan,ZHANG Shifeng,ZHANG Bin,SONG Bo. The Development of the 200 V VDMOS with Large Current[J]. Research & Progress of Solid State Electronics, 2011, 31(1): 85-89 |
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| Authors: | HU Jiaxian HAN Yan ZHANG Shifeng ZHANG Bin SONG Bo |
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| Abstract: | A 200 V/40 A VDMOSFET has been developed.The device introduces a means of JFET implantation and shallow P-body to reduce on-resistance,increase current density,so that to reduce the chip area,and uses n-type silicon epitaxial material to optimize Ron and blocking voltage.The test result indicates that the blocking voltage is above 215 V,the special on-resistance is 1.2 Ω·mm2,the on state current can be up to 40 A,and the HBM of the ESD protection structure is 7.5 kV.The total area of chip is less than 31.25 mm2,so it can be packaged with the type of TO220. |
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| Keywords: | VDMOS large current on-resistance JFET impantation ESD protection |
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