一种提高同步时序PAL结构解析效率的方法

ＰＡＬ器件，尤其是高性能的ＰＡＬ２２Ｖ１０或者２２ＶＰ１０在最新的逻辑电路设计中广泛被采用。国内一些单位曾经做过ＰＡＬ解析方面的工作，但有状态探测时间长，采集数据不准确等缺陷，其解析效果不佳。本文对于同步时序结构的ＰＡＬ器件，提出了一种行之有效的解析方法，它不仅解析速度快，而且可以提高解析的准确性，给研究和分析含有加密的ＰＡＬ器件的逻辑设计者，解决了由于译码不出ＰＡＬ内部码点所带来的一系列困难，并为想要形成ＰＡＬ解析方面产品的用户提供了有效的方法。

METHOD OF ENHANCING EFFICIENCY FOR PAL ARCHITECTURE ANALYSIS IN SYNCHRONOUS SEQUENCE IN TIME

PAL chips, specially PAL22V10 or 22VP10. which have high performance', have been adopted widely in logical circuit design. Someone did some research work in analysing ciphered PAL architecture, but the time is long to search the finite PAL state and the results of experiments are not accurate. This paper gives an efficient method of PAL architecture analysis in synchronous sequence in time. The method can shorten the time exploring the complete PAL finite state, and enhance the accurary for PAL architecture analysis. The method can solve a series of difficulties which can't decipher the fuse codes in PAL for the logical designers who research and analyse digital systems including some ciphered PAL chips, and also gives help to the users who want to develop products on PAL architecture analysis.