基于Boole过程的并行逻辑模拟算法

在逻辑模拟中用波形作为电路状态的描述工具，通过对波形的计算和检查实现精确的模拟。在Boole过程模拟法的基础上，为了降低逻辑模拟计算的时间复杂度，提出了一种基于共享主存结构的借助加权活动元件队列来提高处理机利用率的并行逻辑模拟算法。该算法免除了以往耗时很多的电路划分过程，在一定程度上提高了并行加速比。

Boole Process-Based Parallel Algorithm for Logic Simulation

Waveforms are used as a tool for describing circuits during logic simulation and accurate simulation is achieved by computing and checking waveforms. For reducing time complexity of logic simulation,a parallel algorithm is put forward for logic simulation, which improves the utility rate of processors with Share-Memory Structure and weighted active components queue using the Boole Process-based simulation method. The algorithm avoids the time-consuming design of circuit-partition and improves the parallel acceleration rate to a certain degree.