高性能数字时钟数据恢复电路

设计了一个数字时钟数据恢复电路,采用相位选择锁相环进行相位调整,在不影响系统噪声性能的前提下大大降低了芯片面积。该电路应用于100 MHz以太网收发系统中,采用中芯国际0.18μm标准CMOS工艺实现,核心电路相位选择锁相环的芯片面积小于0.12 mm2,电流消耗低于4 mA。仿真与测试结果表明,恢复时钟抖动的峰峰值小于350 ps,相位偏差小于400 ps,以太网接收误码率小于10-12,电路可以满足接收系统的要求。

A High Performance Digital Clock and Data Recovery Circuit

A digital clock and data recovery circuit is proposed in this paper.A phase selection PLL is adopted to adjust the phase of the recovered clock,and the chip area of the recovery circuit is greatly reduced without sacrificing the noise performance of the system.This circuit is applicated in 100 MHz ethernet transceiver,which is implemented in SMIC 0.18 μm standard CMOS technology.The active area of the core circuit — the phase selection PLL is less than 0.12 mm2,and its current dissipation is less than 4 mA.The simulation and measurement results show that the peak-peak jitter of the recovered clock is less than 350 ps and the phase error is less than 400 ps.The bit error rate of the ethernet receiver is less than 10-12.