Reliability issues in 650V high voltage bipolar-CMOS-DMOS integrated circuits

Dominant failure modes in high power/high voltage (650V) BCD-technologies are threshold voltage instabilities of the lateral DMOS transistor due to sodium ingression and parasitic leakage currents in low voltage devices induced by high surface potentials originating from the high voltage devices. The failure mechanisms and their temperature dependence have been characterized and process and layout improvements are demonstrated.