Single-insertion temperature testing of semiconductor ICs |
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Authors: | Pfahnl A.C. Muller L.A. Cochran P. |
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Affiliation: | Teradyne Inc., Bedford, MA; |
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Abstract: | This paper presents a preliminary-design study considering the feasibility and conceptual implementation of single-insertion temperature testing of any type of semiconductor integrated circuit (IC): memory, microcontroller, microprocessor, or application specific IC. Analyses are presented that establish the necessary thermal response rate of a device under test to make single-insertion testing comparable in throughput performance to a conventional test method. Modeling with ideal conditions to obtain the fastest device response shows that single-insertion testing in testing plastic packaged parts (or slow responding devices) will only be applicable when the test parallelism is very high (>32) and lot overhead times are long (⩾1 h). Given that actual lot overhead times are generally less than 1 h and the trend is for decreasing lot overhead times, the test method is likely more applicable to testing die-exposed type devices, since the test parallelism can be much lower for a given lot overhead time |
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