| Error Detecting Dual Basis Bit Parallel Systolic Multiplication Architecture over GF（2^m） |
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| 作者姓名： | Ashutosh Kumar Singh Asish Bera Hafizur Rahaman Jimson Mathew Dhiraj K.Pradhan |
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| 作者单位： | [1]Dept., School of Engineering, Curtin University of Tcchnology, Malaysia [2]School of VLSI Technology, Bengal Engg. ＆ Sc. University, Shibpur, India [3]Dept. of Information Technology, Bengal Engg. ＆ So. University, Shibpur, India. He is currently visiting University of Bristol, UK. [4]Computer Science Dept., University of Bristol, UK |
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| 基金项目： | Acknowledgment This work has been supported in part by a Royal Society （UK） International Incoming Fellowship awarded to Dr. Hafizur Rahaman. |
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| 摘 要： | An error tolerant hardware efficient verylarge scale integration （VLSI） architecture for bitparallel systolic multiplication over dual base, which canbe pipelined, is presented. Since this architecture has thefeatures of regularity, modularity and unidirectionaldata flow, this structure is well suited to VLSIimplementations. The length of the largest delay pathand area of this architecture are less compared to the bitparallel systolic multiplication architectures reportedearlier. The architecture is implemented using Austria Micro System＇s 0.35 μm CMOS （complementary metaloxide semiconductor） technology. This architecture canalso operate over both the dual-base and polynomialbase.
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| 关 键 词： | 基础架构 线收缩 乘法 错误检测 超大规模集成电路 位并行 CMOS 双基地 |
Error Detecting Dual Basis Bit Parallel Systolic Multiplication Architecture over GF(2m) |
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| Ashutosh Kumar Singh,Asish Bera,Hafizur Rahaman,Jimson Mathew,Dhiraj K.Pradhan.Error Detecting Dual Basis Bit Parallel Systolic Multiplication Architecture over GF(2m)[J].Journal of Electronic Science Technology of China,2009,7(4):336-342. |
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| Authors: | Ashutosh Kumar Singh Asish Bera Hafizur Rahaman Jimson Mathew Dhiraj K Pradhan |
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| Abstract: | An error tolerant hardware efficient very large scale integration (VLSI) architecture for bit parallel systolic multiplication over dual base, which can be pipelined, is presented. Since this architecture has the features of regularity, modularity and unidirectional data flow, this structure is well suited to VLSI implementations. The length of the largest delay path and area of this architecture are less compared to the bit parallel systolic multiplication architectures reported earlier. The architecture is implemented using Austria Micro System's 0.35 μm CMOS (complementary metal oxide semiconductor) technology. This architecture can also operate over both the dual-base and polynomial base. |
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| Keywords: | Bit parallel error correction finite field Reed-Solomon (RS) codes systolic very large scale integration (VLSI) testing |
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