FPGA的多路数据并行录取和时序资源优化

PCIe总线在雷达系统中应用日益广泛,但FPGA内部集成的PCIe硬核数量有限,难以满足雷达并行录取多种数据的需求.为此,本文提出了一种改进的PCIe DMA数据传输方法,利用Xilinx FPGA集成的单个PCIe硬核实现了多路数据在高速传输情况下的并行录取.针对实现过程中遇到的时序问题,提出了采用多级FIFO级联方法进行时序优化.依据Xilinx FPGA的时钟网络特点,对时钟资源进行优化,便于日后系统的扩展和升级.

Parallel Data Transmission Timing and Resource Optimization Based on FPGA

The PCIe bus is widely used in the radar system,but the internal integrated FPGA PCIe core is limited.So ti is difficult to meet the needs of a variety of data parallel transmission of radar.In this paper,an improved PCIe DMA data transmission method is proposed,which ensures the data can be achieved in the parallel high speed transmission using Xilinx FPGA integrated PCIe core.In order to solve the problem of timing in the process of implementation,a multi-level FIFO cascade method is proposed.Based on the characteristics of Xilinx FPGA clock network,the clock resource is optimized for the system expansion and upgrade.