Design of a high-order single-loop Σ△ ADC followed by a decimator in 0.18μm CMOS technology |
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作者姓名: | 李迪 杨银堂 石立春 吴笑峰 |
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作者单位: | School of Microelectronics, Xidian University, Xi 'an 710071, China |
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摘 要: | This work presents an oversampled high-order single-loop single-bit sigma–delta analog-to-digital converter followed by a multi-stage decimation filter.Design details and measurement results for the whole chip are presented for a TSMC 0.18μm CMOS implementation to achieve virtually ideal 16-b performance over a baseband of 640 kHz.The modulator in this work is a fully differential circuit that operates from a single 1.8 V power supply. With an oversampling ratio of 64 and a clock rate of 81.92 MHz,the modulator achieves a 94 dB dynamic range. The decimator achieves a pass-band ripple of less than 0.01 dB,a stop-band attenuation of 80 dB and a transition band from 640 to 740 kHz.The whole chip consumes only 56 mW for a 1.28 MHz output rate and occupies a die area of 1×2 mm^2.
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关 键 词: | CMOS技术 模数转换器 高阶 单回路 模拟数字转换器 设计 芯片面积 delta |
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