| 改进的矩阵求逆的FPGA设计和实现 |
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| 引用本文： | 李颖异. 改进的矩阵求逆的FPGA设计和实现[J]. 中国有线电视, 2006, 0(7): 673-675 |
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| 作者姓名： | 李颖异 |
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| 作者单位： | 电子科技大学,四川,成都,610054 |
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| 摘 要： | 通过对上三角矩阵求逆算法的研究,提出一种优化的适合FPGA实现的并行求逆的结构,并运用Verilog硬件描述语言对其建模,通过硬件仿真工具QuartusII对其进行编译仿真,仿真结果表明,改进的并行结构能够在n个时钟周期内完成n阶上三角矩阵的求逆。
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| 关 键 词： | 三角矩阵 求矩阵逆 |
| 文章编号： | 1007-7022（2006）07-0673-03 |
| 收稿时间： | 2006-01-16 |
| 修稿时间： | 2006-01-16 |
Design and Realization of Improved Matrix''''s Inverse Calculation in FPGA |
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| LI Ying-yi. Design and Realization of Improved Matrix''''s Inverse Calculation in FPGA[J]. China Cable Television, 2006, 0(7): 673-675 |
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| Authors: | LI Ying-yi |
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| Affiliation: | University of Electronic Science and Technology, Sichuan Chengdu 610054, China |
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| Abstract: | This paper introduces an improved parallel structure for FPGA realization due to studying the algorithm of the up-triangle matrix's inverse.The structure is modeled by Verilog HDL,compiled and simulated by QuartusII.The result of the simulation shows that the parallel structure can finish n-order matrix's inverse calculation in n clock periods. |
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| Keywords: | FPGA |
| 本文献已被 CNKI 维普 万方数据 等数据库收录！ |
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