| LDPC码的级联译码算法的改进与实现 |
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| 引用本文： | 陈猛.LDPC码的级联译码算法的改进与实现[J].电子科技,2014,27(6):156-159. |
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| 作者姓名： | 陈猛 |
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| 作者单位： | (中航雷达与电子设备研究院 1部,江苏 无锡 214063) |
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| 摘 要： | 针对中短码长中LDPC码的OSD串行级联译码算法,给出了一种FPGA实现方案。该方案基于FPGA芯片中的块RAM资源,实现了OSD译码中GF(2)上的高斯消元算法,避免了其对逻辑资源的大量消耗。结果表明,该实现方案可在中低端FPGA上实现500 kbit·s-1吞吐量的LDPC码OSD串行级联译码器。
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| 关 键 词： | 信道编码 低密度奇偶校验码 可靠性译码 对数似然比累积 现场可编程门阵列 |
Improvement and Implementation of Concatenated Decoding for LDPC Codes |
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| CHEN Meng.Improvement and Implementation of Concatenated Decoding for LDPC Codes[J].Electronic Science and Technology,2014,27(6):156-159. |
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| Authors: | CHEN Meng |
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| Affiliation: | (No.1 Department,Radar and Electronic Equipment Research Institute of Aviation Industry Corporation,Wuxi 214063,China) |
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| Abstract: | An FPGA implementation scheme for the OSD serially concatenated decoding algorithms is proposed for LDPC codes with short or moderate code length. Our scheme implements the GF（2） Gaussian elimination used in OSD algorithm based on the block RAM resource of the FPGA chip, which avoids the large quantity of logic resource demand for the conventional implementation of GF （2） Gaussian elimination. Implementation result shows that the concatenated decoder with 500 kbit · s^-1 throughput can be achieved on middle and low grade FPGA using this scheme. |
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| Keywords: | channel coding low density parity-check code reliability decoding log-likelihood ratio accumu-lation field programmable gate arrays |
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