| 弹性分组环专用集成电路的可测性设计 |
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| 引用本文： | 张凡,李济世,陈虹,金德鹏,曾烈光. 弹性分组环专用集成电路的可测性设计[J]. 微电子学, 2006, 36(2): 197-200 |
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| 作者姓名： | 张凡 李济世 陈虹 金德鹏 曾烈光 |
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| 作者单位： | 清华大学,电子工程系,通信与微波重点实验室,北京,100084 |
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| 基金项目： | 国家高技术研究发展(863)计划资助项目(2002AA121041) |
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| 摘 要： | 根据弹性分组环专用集成电路的具体情况,提出了相应的可测性设计(Design for Test-ability,DFT)方案,综合运用了三种DFT技术:扫描链、边界扫描测试和存储器内建自测试。介绍了三种技术的选取理由和原理,对其具体实现过程和结果进行了详细分析。DFT电路的实现大大降低了专用集成电路的测试难度,提高了故障覆盖率。
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| 关 键 词： | 弹性分组环 专用集成电路 可测性设计 扫描链 边界扫描测试 存储器内建自测试 |
| 文章编号： | 1004-3365（2006）02-0197-04 |
| 收稿时间： | 2005-06-20 |
| 修稿时间： | 2005-06-202005-08-23 |
Design for Testability of a Resilient Packet Ring ASIC |
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| ZHANG Fan,LI Ji-shi,CHEN Hong,JIN De-peng,ZENG Lie-guang. Design for Testability of a Resilient Packet Ring ASIC[J]. Microelectronics, 2006, 36(2): 197-200 |
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| Authors: | ZHANG Fan LI Ji-shi CHEN Hong JIN De-peng ZENG Lie-guang |
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| Abstract: | Based on the practical test requirements of resilient packet ring(RPR) ASIC,a design for Testability(DFT) strategy is presented,in which three different DFT methods are used.Principles and key methods used in the strategy are described,including scan chain,boundary scan test(BST),and memory built-in-self-test(MBIST).Implementation process and results of the DFT strategy are analyzed in detail.DFT circuits implemented in RPR ASIC reduces difficulties in circuit test and greatly improves fault coverage. |
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| Keywords: | Resilient packet ring Design for testability Scan chain Boundary scan test MBIST |
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