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Synchronization coherence: A transparent hardware mechanism for cache coherence and fine-grained synchronization |
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| Authors: | Yao Guo Vladimir Vlassov Raksit Ashok Richard Weiss Csaba Andras Moritz |
| Affiliation: | 1. School of Electronics Engineering and Computer Science, Peking University, Beijing 100871, China;2. School of Information and Communication Technology, Royal Institute of Technology, Sweden;3. Google Inc., 1600 Amphitheatre Parkway, Mountain View, CA 94043, USA;4. The Evergreen State College, Olympia, WA 98505, USA;5. Department of Electrical and Computer Engineering, University of Massachusetts, Amherst, MA 01003, USA |
| Abstract: | The quest to improve performance forces designers to explore finer-grained multiprocessor machines. Ever increasing chip densities based on CMOS improvements fuel research in highly parallel chip multiprocessors with 100s of processing elements. With such increasing levels of parallelism, synchronization is set to become a major performance bottleneck and efficient support for synchronization an important design criterion. Previous research has shown that integrating support for fine-grained synchronization can have significant performance benefits compared to traditional coarse-grained synchronization. Not much progress has been made in supporting fine-grained synchronization transparently to processor nodes: a key reason perhaps why wide adoption has not followed. |
| Keywords: | Cache coherence Fine-grained synchronization Energy efficiency |
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