一种宽带高性能TIADC时钟发生器

针对并行交替模拟数字转换器(TIADC)发展遇到的时钟瓶颈,提出了一种宽带高性能TIADC时钟发生器设计方案.该方案利用时钟分路器和可编程延迟器分别实现通道扩展和相位延迟,采用可配置时钟源和逻辑转换电路使时钟发生器能够输出低抖动的CMOS和ECL逻辑TIADC时钟.设计实现的时钟发生嚣已经成功用于4通道12 bit 320 MHz采样率的TIADC系统.测试结果表明,该时钟发生器具有10 ps延迟偏差和在80MHz频率下不超过2 ps的时钟抖动.

Design and Implementation of Wideband High-Performance TIADC Clock Generator

To solve the clock limitations of time-interleaved analog-to-digital converter (TIADC),a solution of wideband high-performance TIADC clock generator is proposed.The clock distributor and the programmable delayer are used to transfer the global clock into multichannel clocks and set multiphase clocks for each sub-ADCs accordingly.Furthermore,a configurable clock source and the ECL propagation logic with ECL-CMOS transfer circuits are designed to output both ECL and CMOS clock with low jitter for the sub-ADCs of TIADC system.The example design is used in a 4 channel 12 bit 320 M sampling per second TIADC system.Experimental results indicate that the designed clock generator can generate the CMOS/ECL clocks for the TIADC system with 10 ps time-skew mismatch and the clock jitter is smaller 2 ps at 80 MHz.