Extremely scaled 3-dimensional multiple-gate technologies for terabit era |
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Authors: | Choi Yang-Kyu Kim Kuk-Hwan Han Jin-Woo Ryu Seong-Wan Lee Hyunjin |
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Affiliation: | School of Electrical and Computer Science, Division of Electrical Engineering, Korea Advanced Institute of Science and Technology, 373-1, Daejeon 305-701, Korea. |
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Abstract: | In order to make possible silicon-based, room-temperature operable devices having a feature size in the sub-5 nm range, an all-around gate FinFET having an extremely narrow gate-surrounded silicon fin with a floating body was proposed and fabricated. Sub-10 nm device issues such as short channel effects, punchthrough, source/drain series resistance, gate misalignment, and hot-carrier injection were intensively studied and optimized for the sub-5 nm structure. The sub-5 nm all-around gate FinFET with 3 nm fin width and 1.2 nm EOT was demonstrated for the first time. |
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