Device characteristics improvement of a-In-Ga-Zn-O TFTs by low-temperature annealing |
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Authors: | Yutomo Kikuchi Kenji Nomura Toshio Kamiya Masahiro Hirano |
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Affiliation: | a Materials and Structures Laboratory, Tokyo Institute of Technology, 4259 Nagatsuta, Midori-ku, Yokohama 226-8503, Japan b ERATO-SORST, JST, 4259 Nagatsuta, Midori-ku, Yokohama 226-8503, Japan c Frontier Research Center, Tokyo Institute of Technology, 4259, Nagatsuta, Midori-ku, Yokohama 226-8503, Japan |
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Abstract: | A low-temperature process to improve performances of a-In-Ga-Zn-O (a-IGZO) thin-film transistors (TFTs) fabricated at room temperature was examined. Two deposition methods, pulsed laser deposition (PLD) and RF magnetron sputtering were employed to deposit the a-IGZO channels. For the PLD case, the TFT characteristics were improved significantly by wet annealing at dew point (d.p.) of 50 °C at the annealing temperature of 200 °C. For the sputtered TFTs, a wider range of annealing temperature from 100 to 200 °C was examined. It was found that annealing at ≥ 150 °C improved the TFT characteristics when dry annealing was employed. On the other hand, wet annealing also improved μsat and S values, but very large negative threshold voltage (Vth) shift was observed. These results indicate that the annealing at 150 °C is enough to obtain mobility (μsat) as large as 8 cm2 Vs− 1, but annealing temperature as high as 200 °C provides larger μsat comparable to those obtained by 400 °C annealing. It is speculated that the large negative Vth shift originates from compensated donors in as-deposited sputtered films. |
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Keywords: | Thin-film transistor Amorphous oxide semiconductor a-IGZO Low-temperature annealing |
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