| ASIC Design of High-Speed Low-Power HDLC Controller |
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| 作者姓名： | 陈禾 韩月秋 |
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| 作者单位： | Department of Electronic Engineering，School of Information Science and Technology，Beijing Institute of Technology，Beijing 100081，China，Department of Electronic Engineering，School of Information Science and Technology，Beijing Institute of Technology，Beijing 100081，China |
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| 基金项目： | the Ministerial Level Foundation(1407327) |
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| 摘 要： | Combined with the engineering requirement, a high-speed low-power ASIC design of HDLC controllerbased on RS-485 bus is given in this paper.On principle of Top-Down design, this ASIC design usesmulti-techniques to reduce its die area and dynamic power,and overcomes some problems appeared frequently inapplication systems of the RS-485 circuits formed by the Standard Interface Chips. This design also improves thesystem reliability and reduces the system area.
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ASIC Design of High-Speed Low-Power HDLC Controller |
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| CHEN He HAN Yue-qiu.ASIC Design of High-Speed Low-Power HDLC Controller[J].Journal of Beijing Institute of Technology,2003(Z1). |
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| Authors: | CHEN He HAN Yue-qiu |
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| Abstract: | Combined with the engineering requirement, a high-speed low-power ASIC design of HDLC controller based on RS-485 bus is given in this paper. On principle of Top-Down design, this ASIC design uses multi-techniques to reduce its die area and dynamic power, and overcomes some problems appeared frequently in application systems of the RS-485 circuits formed by the Standard Interface Chips. This design also improves the system reliability and reduces the system area. |
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| Keywords: | HDLC ASIC RS-485 bus communication controller |
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